EVAL-AD7322CB1【PDF 9/18 页】Software Selectable True Bipolar Input,

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Preliminary Technical Data

AD7322

the selected channel with a 50 kHz signal. The figure given is

the worst-case across all eight channels for the AD7322.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with non-linearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those

for which neither m nor n are equal to zero. For example, the

second order terms include (fa + fb) and (fa – fb), while the

third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa

– 2fb).

The AD7322 is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second order terms are usually distanced in

frequency from the original sine waves while the third order

terms are usually at a frequency close to the input frequencies.

As a result, the second and third order terms are specified

separately. The calculation of the intermodulation distortion is

as per the THD specification where it is the ratio of the rms

sum of the individual distortion products to the rms amplitude

of the sum of the fundamentals expressed in dBs.

PSR (Power Supply Rejection)

Variations in power supply will affect the full-scale transition

but not the converter’s linearity. Power supply rejection is the

maximum change in full-scale transition point due to a change

in power supply voltage from the nominal value. See Typical

Performance Curves.

Theory of Operation

CIRCUIT INFORMATION

The AD7322 is a fast, 2-Channel, 12-bit plus Sign, Bipolar Input,

Serial A/D converter. The AD7322 can accept bipolar input

ranges that include ±10V, ±5V, ±2.5V, it can also accept 0 to 10V

unipolar input range. Different Analog input ranges can be

programmed on each analog input Channel via the on-chip

range register. The AD7322 has a high speed serial interface that

can operate at throughput rates up to 1 MSPS.

The AD7322 requires V

and V

dual

supplies for the high

voltage Analog input structure. These supplies must be equal to

or greater than the Analog input range. See

minimum requirements on these supplies for each Analog Input

Range. The AD7322 requires a low voltage 2.7V to 5.25 V V

supply to power the ADC core.

for the

Table 5

Table 5. Reference and Supply Requirements for each Analog

Input Range

Ain Range

Min

Reference V

± 12 V

3 V to 5V

± 10 V

± 10V

3 V to 5 V

2.5 V

± 5 V

3V to 5V

2.5 V

± 2.5 V

± 5 V

3 V to 5 V

2.5 V

0 to 10 V

± 10 V

3 V to 5 V

2.5 V

The Analog Inputs can be configured as either 2 Single-Ended

inputs, 1 True Differential Inputs, or 1 Pseudo Differential

Input. Selection can be made by programming the Mode bits,

Mode0 and Mode1, in the on-chip Control Register.

The serial clock input accesses data from the part but also

provides the clock source for each successive approximation

ADC. The AD7322 has an on-chip 2.5 V reference. If an

External Reference is the preferred option the user must write

to the reference bit in the control register to disable the internal

Reference.

The AD7322 also features power-down options to allow power

saving between conversions. The power-down modes are

selected by programming the power management bits in the on-

chip Control Register, as described in the Modes of Operation

section.

CONVERTER OPERATION

The AD7322 is a successive approximation analog-to-digital

converter, based around two capacitive DACs. F

show simplified schematics of the ADCs in Single

Ended Mode during the acquisition and conversion phase,

respectively.

and Fi

of the ADC in Differential Mode during acquisition and

conversion phase, respectively. The ADC is comprised of

control logic, a SAR, and a capacitive DAC. In F

acquisition phase), SW2 is closed and SW1 is in position A, the

comparator is held in a balanced condition, and the sampling

capacitor array acquires the signal on the input.

and

show simplified schematics

(the

igure 4

Figure 4. ADC Acquisition Phase(Single Ended)

Figure 5

Figure 6

gure 7

Rev. PrE | Page 9 of 18

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